1. Field of the Invention
This invention relates to core memories and more particularly to small core memories utilizing feedback from an auxiliary timing core to economically optimize sensing and drive times without complicated close toleranced drive circuits.
2. Discussion of the Prior Art
Magnetic core memories utilize arrays of square hysteresis loop memory cores which are selectively switched from one state of magnetization to another to store a given data condition. Data readout is accomplished by switching a selected core toward a given state. If the core switches and therefore produces a substantial output switching voltage signal it is determined to have stored a "one". If the core was already in the given state and therefore does not switch it is determined to have stored a "zero".
Sensing is complicated by changes in the switching signal with ambient conditions and by noise signals which accompany the switching signal. The noise signals, which are caused by the coupling of drive currents into the sense windings and from unbalanced delta noise induced in unselected cores receiving a partial select drive current, tend to occur early with respect to a core output switching signal. The magnitude tends to decrease rapidly toward zero as the read part cycle progresses. The noise can thus be distinguished from the switching signal by generating a strobe signal to command the sensing of the output switching signal at a time subsequent to the noise signal peak but soon enough that the switching signal magnitude is still substantial. Sensing occurs relative to a voltage threshold which must be sufficiently high to distinguish over any noise remaining on the sense windings at the time of the strobe signals yet sufficiently low that a valid output switching signal will remain above the threshold for sufficient time following the strobe signal to permit detection.
Changes in drive current magnitude greatly affect the nature of the noise signals and core switching signals. High drive currents tend to produce fast peaking, large magnitude signals with fast switching times while low drive currents tend to produce slow peaking, low magnitude signals with long switching times. Temperature changes tend to have similar effects with the exact relationship dependent upon the composition of the particular type of core that is used.
It is thus seen that for high drive conditions, the strobe time should occur early relative to the drive current rise time and the threshold should be relatively high to distinguish the relatively large noise signal that will remain at the early time even with a large drive current. However, with an early strobe and high voltage threshold, a low drive current or corresponding temperature condition may preclude proper separation of the core switching signal from the noise. The delayed timing and small magnitude of the switching peak may cause the switching signal to fail to exceed the reference voltage at the time of the strobe, thus causing a "one" to be sensed as a "zero". Alternatively, the noise may be of sufficient duration and magnitude to be sensed as a "one" irrespective of the actual data state of a selected core.
To assure proper sensing, core memories have traditionally employed high quality current drivers with tolerances on the order of plus or minus 10-15%. Frequently the drive currents are varied in response to sensed core temperature conditions to compensate for the corresponding changes in core switching characteristics. Drive current duration times must be established sufficiently long to accommodate worst case (low drive) conditions. Under high drive conditions the drive current duration is thus longer than necessary, thus wasting power and subjecting partially selected cores to disturb currents for longer than necessary.